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rev 1.2 12/15 copyright ? 2015 by silicon laboratories SI52111-B5/b6 SI52111-B5/b6 pci-e xpress g en 3 s ingle o utput c lock g enerator features applications description SI52111-B5/b6 is a high-performance, pcie clock generator that can source one pcie clock output from a 25 mhz crystal or clock input. the clock output is compliant to pcie gen 1, gen 2, gen 3, gen 3 srns and gen 4 common clock specifications. the ultra-small footprint (3x3 mm) and industry leading low power consumption make SI52111-B5/b6 the ideal clock solution for consumer and embedded applications. measuring pcie clock jitter is quick and easy wit h the silicon labs pcie clock jitter tool. download it for free at www.silabs.com/pcie-learningcenter . functional block diagram ? pci-express gen 1, gen 2, gen 3, and gen 4 common clock compliant ? gen 3 srns compliant ? low power hcsl differential output buffer ? supports serial-ata (sata) at 100 mhz ? no termination resistors required ? 25 mhz crystal input or clock input ? triangular spread spectrum profile for maximum emi reduction (si52111-b6) ? extended temperature: ?40 to 85 c ? 3.3 v power supply ? small package 10-pin tdfn (3x3 mm) ? SI52111-B5 does not support spread spectrum outputs ? si52111-b6 supports 0.5% down spread outputs ? network attached storage ? multi-function printer ? wireless access point ? routers xin/clkin xout diff1 pll divider vdd vss patents pending ordering information: see page 13 pin assignments 10 9 8 7 1 2 3 4 vdd nc nc vdd xout xin/clkin vss vss 5 6 diff1 diff1
SI52111-B5/b6 2 rev 1.2
SI52111-B5/b6 rev 1.2 3 t able of c ontents section page 1. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. crystal recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1. crystal loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2. calculating load capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3. test and measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1. 10-pin tdfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2. 8-pin tssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6. package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1. tdfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2. tssop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7. recommended design guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SI52111-B5/b6 4 rev 1.2 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit supply voltage (extended) v dd(extended) 3.3 v 5% 3.13 3.3 3.46 v supply voltage (commercial) v dd(commercial) 3.3 v 10% 2.97 3.3 3.63 v table 2. dc electrical specifications parameter symbol test condition min typ max unit operating voltage v dd 3.3 v 10% 2.97 3.30 3.63 v operating supply current i dd full active ? ? 13 ma input pin capacitance c in input pin capacitance ? 3 5 pf output pin capacitance c out output pin capacitance ? ? 5 pf table 3. ac electrical specifications parameter symbol test condition min typ max unit crystal long-term accuracy l acc measured at v dd /2 differential ? ? 250 ppm clock input clkin duty cycle t dc measured at v dd /2 45 ? 55 % clkin rise and fall times t r /t f measured between 0.2 v dd and 0.8 v dd 0.5 ? 4.0 v/ns clkin cycle-to-cycle jitter t ccj measured at v dd /2 ? ? 250 ps clkin long term jitter t ltj measured at v dd /2 ? ? 350 ps input high voltage v ih xin/clkin pin 2 ? v dd +0.3 v input low voltage v il xin/clkin pin ? ? 0.8 v input high current i ih xin/clkin pin, vin = v dd ?? 35ua input low current i il xin/clkin pin, 0 < vin <0.8 ?35 ? ? ua diff clocks duty cycle t dc measured at 0 v differential 45 ? 55 % skew t skew measured at 0 v differential ? ? 60 ps output frequency f out vdd = 3.3 v ? 100 ? mhz frequency accuracy f acc all output clocks ?? 100 ppm slew rate t r/f2 measured differentially from 150 mv 0.6 ? 4.0 v/ns notes: 1. visit www.pcisig.com for complete pcie specifications. 2. gen 4 specifications based on the pci-ex press base specification 4.0 rev. 0.5 3. download the silicon labs pcie clock jitter tool at www.silabs.com/pcie-learningcenter .
SI52111-B5/b6 rev 1.2 5 cycle-to-cycle jitter t ccj measured at 0 v differential ? 28 70 ps pcie gen 1 pk-pk jitter, common clock pk-pk gen1 pcie gen 1 ?24 86 ps pcie gen 2 phase jitter, common clock rms gen2 10 khz < f < 1.5 mhz ? 1.35 3.0 ps 1.5 mhz < f < nyquist ? 1.4 3.1 ps pcie gen 3 phase jitter, common clock rms gen3 includes pll bw 2?4 mhz, cdr = 10 mhz ?0.4 1.0 ps pcie gen 3 phase jitter, separate reference no spread, srns rms gen3_srns pll bw of 2?4 or 2?5 mhz, cdr = 10 mhz ? 0.28 0.71 ps pcie gen 4 phase jitter, common clock rms gen4 pll bw of 2?4 or 2?5 mhz, cdr = 10 mhz ?0.4 1.0 ps crossing point voltage at 0.7 v swing v ox 300 ? 550 mv voltage high v high ? ? 1.15 v voltage low v low ?0.3 ? ? v spread range s rng down spread, -b6 only ? ?0.5 ? % modulation frequency f mod -b6 only 30 31.5 33 khz enable/disable and set-up clock stabilization from power-up t stable ?? 3 ms stopclock set-up time t ss 10.0 ? ? ns table 3. ac electrical specifications (continued) parameter symbol test condition min typ max unit notes: 1. visit www.pcisig.com for complete pcie specifications. 2. gen 4 specifications based on the pci-ex press base specification 4.0 rev. 0.5 3. download the silicon labs pcie clock jitter tool at www.silabs.com/pcie-learningcenter .
SI52111-B5/b6 6 rev 1.2 table 4. thermal conditions parameter symbol test condition min typ max unit temperature, storage t s non-functional ?65 ? 150 c temperature, operating ambient t a functional ?40 ? 85 c temperature, junction t j functional ? ? 150 c dissipation, junction to case (tdfn) ? jc jedec (jesd 51) ? ? 38.3 c/w dissipation, junction to case (tssop) ? jc jedec (jesd 51) ? ? 37.0 c/w dissipation, junction to ambient (tdfn) ? ja jedec (jesd 51) ? ? 90.4 c/w dissipation, junction to ambient (tssop) ? ja jedec (jesd 51) ? ? 124.0 c/w table 5. absolute maximum conditions parameter symbol test condition min typ max unit main supply voltage v dd_3.3v ?4.6v input voltage v in relative to v ss ?0.5 4.6 v dc esd protection (human body model) esd hbm jedec (jesd 22 - a114) 2000 ? v flammability rating ul-94 ul (class) v?0 note: while using multiple power supplies, the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required .
SI52111-B5/b6 rev 1.2 7 2. crystal recommendations if using a crystal input, the device requires a parallel resonance crystal. 2.1. crystal loading crystal loading is critical in achieving low ppm perfo rmance. to realize low ppm performance, use the total capacitance the crystal sees to calculate the appropriate capacitive loading (cl). figure 1 shows a typical crystal configuration using two trim ca pacitors. it is important that the trim capacitors are in series with the crystal. figure 1. crystal capacitive clarification table 6. crystal recommendations frequency (fund) cut loading load cap esr drive shunt cap (max) motional (max) tolerance (max) stability (max) aging (max) 25 mhz at parallel 12?15 pf <50 ? >150 w 5 pf 0.016 pf 35 ppm 30 ppm 5 ppm
SI52111-B5/b6 8 rev 1.2 2.2. calculating load capacitors in addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate the crystal loading correctly. again, the capacitance on each side is in series with the crystal. the total capacitance on both sides is twice the specified crystal load capacitance (cl). trim capacitors are calculated to provide equal capacitive loading on both sides. figure 2. crystal loading example use the following formulas to calculate the trim capacitor values for ce1 and ce2. load capacitance (each side) total capacitance (as seen by the crystal) ?? cl: crystal load capacitance ?? cle: actual loading seen by crystal using standard value trim capacitors ?? ce: external trim capacitors ?? cs: stray capacitance (terraced) ?? ci: internal capacitance (lead frame, bond wires, etc.) ce 2 cl cs ci + ?? ? ? = cle 1 1 ce1 cs1 ci1 ++ --------------------------------------------- 1 ce2 cs2 ci2 ++ --------------------------------------------- + ?? ?? ------------------------------------------------------------------------------------------------------- =
SI52111-B5/b6 rev 1.2 9 3. test and measurement setup figures 3 through 5 show the test load conf iguration for the differential clock signals. figure 3. 0.7 v differential load configuration figure 4. differential measurement for differential output signals (for ac parameters measurement) measurement point 2pf 50 ? measurement point 2pf 50 ? l1 l1 = 5" out+ out- l1
SI52111-B5/b6 10 rev 1.2 figure 5. single-ended measurement for differential output signals (for ac parameters measurement)
SI52111-B5/b6 rev 1.2 11 4. pin descriptions 4.1. 10-pin tdfn figure 6. 10-pin tdfn table 7. 10-pin tdfn descriptions pin # name type description 1vdd pwr 3.3 v power supply. 2xout o 25.00 mhz crystal output, float xout if using only clkin (clock input). 3 xin/clkin i 25.00 mhz crystal input or 3.3 v, 25 mhz clock input. 4 vss gnd ground. 5 vss gnd ground. 6 diff1 o, dif 0.7 v, 100 mhz differentials clock output. 7 diff1 o, dif 0.7 v, 100 mhz differentials clock output. 8nc nc no connect. do not connect this pin to anything. 9nc nc no connect. do not connect this pin to anything. 10 vdd pwr 3.3 v power supply 10 9 8 7 1 2 3 4 vdd nc nc vdd xout xin/clkin vss vss 5 6 diff1 diff1
SI52111-B5/b6 12 rev 1.2 4.2. 8-pin tssop figure 7. 8-pin tssop table 8. 8-pin tssop descriptions pin # name type description 1vdd pwr 3.3 v power supply. 2xout o 25.00 mhz crystal output, float xout if using only clkin (clock input). 3 xin/clkin i 25.00 mhz crystal input or 3.3 v, 25 mhz clock input. 4 vss gnd ground. 5 diff1 o, dif 0.7 v, 100 mhz differentials clock. 6 diff1 o, dif 0.7 v, 100 mhz differentials clock. 7nc no connect. do not connect this pin to anything. 8nc no connect. do not connect this pin to anything. 8 si52111 7 6 5 nc nc diff1 diff1 vdd xout xin/clkin vss 1 2 3 4
SI52111-B5/b6 rev 1.2 13 5. ordering guide figure 8. ordering information part number spread option package type temperature SI52111-B5-gm2 no spread 10-pin tdfn extended, ?40 to 85 c SI52111-B5-gm2r no spread 10-pin tdfn?tape and reel extended, ?40 to 85 c SI52111-B5-gt no spread 8-pin tssop extended, ?40 to 85 c SI52111-B5-gtr no spread 8-pin tssop - tape and reel extended, ?40 to 85 c si52111-b6-gm2 ?0.5% spread 10-pin tdfn extended, ?40 to 85 c si52111-b6-gm2r ?0.5% spread 10-pin tdfn?tape and reel extended, ?40 to 85 c si52111-b6-gt ?0.5% spread 8-pin tssop extended, ?40 to 85 c si52111-b6-gtr ?0.5% spread 8-pin tssop - tape and reel extended, ?40 to 85 c si52111 bx gm2r/gtr base part number b: product revision b x=5: non spread outputs x=6: -0.5% spread outputs operating temp range: g: -40 to +85 c m2 :10-tdfn package, rohs6, pb-free t: 8-tssop package, rohs6, pb-free r: tape & reel (blank) = tubes
SI52111-B5/b6 14 rev 1.2 6. package outlines 6.1. tdfn package figure 9 illustrates the package details for the 10-pin tdfn . table 9 lists the values for the dimensions shown in the illustration. figure 9. 10-pin tdfn package drawing
SI52111-B5/b6 rev 1.2 15 table 9. tdfn package diagram dimensions symbol min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 ref. b 0.18 0.25 0.30 d 3.00 bsc. d2 1.90 2.00 2.10 e0.50 bsc e3.00 bsc e2 1.40 1.50 1.60 l 0.25 0.30 0.35 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.10 eee 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. 4. this drawing conforms to the jedec solid state outline mo-229.
SI52111-B5/b6 16 rev 1.2 6.2. tssop package figure 10 illustrates the package details for the 8-pin tssop. table 10 lists th e values for the di mensions shown in the illustration. figure 10. 8-pin tssop package drawing
SI52111-B5/b6 rev 1.2 17 table 10. tssop package diagram dimensions symbol min nom max a? ?1.20 a1 0.05 ? 0.15 a2 0.80 0.90 1.05 b 0.19 ? 0.30 c 0.09 ? 0.20 d 2.90 3.00 3.10 e6.40 bsc e1 4.30 4.40 4.50 e0.65 bsc l 0.45 0.60 0.75 l2 0.25 bsc 0 ? 8 aaa 0.10 bbb 0.10 ccc 0.05 ddd 0.20 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the je dec solid state outline mo-153, variation aa. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
SI52111-B5/b6 18 rev 1.2 7. recommended design guideline figure 11. recommended application schematic note: fb specifications: dc resistance 0.1?0.3 ? impedance at 100 mhz > 1000 ? 3.3 v 4.7 f 0.1 f vdd si5211x
SI52111-B5/b6 rev 1.2 19 d ocument c hange l ist revision 1.0 to revision 1.1 ? added ?4.2. 8-pin tssop? pin description on page 12. revision 1.1 to revision 1.2 ? updated features on page 1. ? updated description on page 1. ? updated table 3, ?ac electrical specifications,? on page 4.
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